Parasitic effects are becoming more pronounced with the advent of deep submicron process technologies. Parasitic capacitances, parasitic resistances and parasitic inductances are commonly called parasitic devices, parasitic components, or simply parasitics. Even though the recent processing technology advancements of copper interconnect reduces the effect of parasitic resistance and the low k (<3) dielectric material reduces the effect of parasitic capacitance, the continued scaling down of the feature size keeps the parasitic effects dominant, and makes it a necessity to account accurately for parasitic effects for large and complicated interconnect structures.
To account for parasitic effects in both designed devices and required wiring interconnects of an electronic circuit, parasitic extraction needs not only information of a design itself such as the top view layout of the design in the form of input polygons on a set of layers, a mapping to a set of devices and pins (derived using a layout-versus-schematic (LVS) tool), and a cross sectional understanding of these layers, but also process calibration data. Process calibration data are tied to manufacturing processes and are supplied to designers by manufacturers. A manufacturer typically runs simulations on a large number of test structures to obtain process calibration data for various patterns in the form of empirical formulas, look-up tables or both, which is sometimes referred to as a pattern library. A parasitic extraction tool can then extract geometric parameters of layout features from the layout design and calculate parasitic values based on the extracted geometric parameters and the process calibration data.
As the number of transistors increases, the number of nets in the design increases proportionally. This means process calibration data also increase significantly, resulting in an increase in parasitic extraction runtime and memory capacity requirement. Moreover, process calibration data often contain proprietary technology information which a manufacturer often wants to keep from disclosing. Accordingly, process calibration data are usually encrypted before being supplied to designers. The encryption further slows down a parasitic extraction process. A compact representation of process calibration data that addresses these challenges (extraction runtime, memory capacity and encryption) is highly desirable.